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PCB Design For Beginners: Ugly Tracks Are Noisy

Electron Injection

132,507 views

I laid out dozens and dozens of PCBs (printed circuit boards) and could never figure out why my tracks always looked crappy. It turns out that laying out "pretty" PCB tracks is just as much function as it is form. It's all a function of capacitive coupling. The short version goes likes this. If you want noise to jump from one track to another, put the tracks as close as possible. Obviously, almost no one wants that. So, we spread them out. When we spread them out equally and minimize the amount of space in which traces come in close contact, we end up with pretty tracks and a low-noise layout.

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20 Comments

@brylozketrzyn 3 years ago

One thought. If your design has signals much slower than 30MHz and has four layers - your actual coupling will be miniscule. It may create some crosstalk but not as strong to make digital glitch. For very sensitive analog signals passive or active guarding (depending on your source internal resistance is a must). And then you will face signals so weak, that surface resistance of FR4 will make them offset by tens of milivolts. This is when the fun starts. I've been working on contactless ECG electrodes. Exotic PCB materials, low bias opamps, double guarding. But their noise level was lower, than classic silver chloride ones.

@zDoubleE23 2 years ago

Holy crap! I went to school with you! I even revised/updated your KiCad tutorial that you made for Dr. R!! Wow!! I’m glad you’re still at it!

@dextertech6570 3 years ago

I don't know what C9 is for, but i believe it doing some decent job and very critical

@douglasstrother6584 11 months ago

"High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices" by Stephen H. Hall, Garrett W. Hall & James A. McCall is very informative.

@georgewyatt9365 2 years ago

Crosstalk depends on the length of your tracks and the distance of the track from the ground plane, for a track as short as that I can't see any issue even with fast CMOS, best to use a cross-talk calculator and a practical experiment to prove this. The main goal in most PCB design exercises is to reduce current "loop area" with short tracks and ground planes. A "good looking" board is is a functional one, tracking isn't cosmetic. Your layer stack-up is also a little odd. I recommend Rob Feranec and Eric Bogatin's PCB lectures for anyone that wants to get into PCB tracking.

@Electheo 3 years ago

Nice work! If I may make a remark: prevent copper angles sharper than 90 degrees. I consider them ugly. They can create noise/EMI, depending on the frequencies. At high voltages (like 1 kV) these sharp angles can create arcs as well.
This all may be beside the point you’re making, but worth mentioning :)

@gustavo9758 3 weeks ago

"no thought required"

This is my jam!

@adamnowak8876 2 years ago

Beautiful acid traps. Keep up the good work :)

@andreaslack8379 5 days ago

"Equal spacing" when it is pretty clear the spacing is unequal. I don't know if there is a grid to keep things orderly. Every PCB I've done from pencil and tape through every PCB software had a grid and picking a good grid is a key to neatness, and even spacing. I really I can't imagine a digital signal given what looks like a SOIC where cross coupling of digital is going to be a problem. The whole point of digital is to have immunity from noise. You are correct GHz level signals will need some attention but then there are other factors to worry about than just spacing.

@fano72 2 years ago

Sharp edges are ugly, too. They act like antennas.

@mariomations5800 4 months ago

so no one is going to talk about the c9 at 0:25

@xavierr4508 1 year ago

In 2:31 you've mentioned that KiCAD doesn't have push mode; it has: Interactive router settings (Ctrl + <), then "Shove". I've been using it for years, maybe before KiCAD 7.

@marienverx1852 3 years ago

Quite right... I did clean the routing a lot tot make is very poper. But making the routing chaotic results in less crosstalk problems..

@marcdraco 1 year ago

I know I'm a bit late to the party but the edge times (rise and fall) are what matters here. The clock speed could be 1 Hz for all the difference it makes, it's the edge that determines the frequency and you have to think of at least nine harmonics above that to realise what sort of frequencies you're really dealing with. Even "slow" chips can have rise times in the sub-nano second time now and even track length can become a factor where critical timing is an issue as the signal (the fields) have to arrive at more or less the same time.

The electric field (capacitive coupling) is very weak and has a precious little range - it's the inductive coupling (magnetic field) that you need to worry about. Most of this can be contained with a solid ground plane as close to the top layer as possible.

@CarlsTechShed 3 years ago

Great video and well explained. Personally, I'd have rotated U2 by 90 degrees counter-clockwise so that the pins connected to J4 will be (mostly) parallel with their destination. Pin 8 on U2 will still need to be routed underneath the IC as it is now but it'd just look a bit neater 🙂

@isaactippetts3202 11 months ago

This guy is tango tek if he did circuits instead of redstone. Very much a compliment. Loved watching this, I'll sub and see more of your vids.

@MikeZ8709 1 year ago

In a video of an MRI of a Thunderbolt cable, it showed some [i think microscopic] tracks that were intentionally zigg-zagged to make their length equal with the other tracks.